This invention relates to serializer circuitry for integrated circuits such as programmable logic device integrated circuits, and more particularly, to integrated circuits and serializer circuitry with two-phase serializer master clock generators.
Serial communications links are often used in modern electronics systems. Serial communications links use fewer pins than parallel links, and, particularly when differential signaling schemes are used, serial links support high speeds and exhibit good noise immunity.
Digital integrated circuits typically handle internal data processing functions using parallel data. For example, one logic circuit on a digital integrated circuit may provide data to another logic circuit over an eight bit or sixteen bit bus.
When it is desired to transmit parallel data from a digital integrated circuit to another integrated circuit over a serial link, the parallel data must be converted to a serial format. Parallel-to-serial data conversion is handled using serializers. A serializer has multiple inputs that receive parallel data from a data bus. The serializer converts the parallel data on its inputs to serial data. The serial data is provided on an output. In a typical arrangement, the serial data on the output is provided to a differential output driver that transmits the serial data to a receiver over a differential signal path.
As integrated circuits become more complex, there is an interest in supporting increasingly large serial link data rates. However, the timing margins provided by conventional serializer architectures may not be sufficient to reliably compensate for clock skew and jitter in high data-rate environments.
It is therefore an object of the present invention to provide ways in which to implement robust serializer circuitry for integrated circuits such as programmable logic device integrated circuits.